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| ds07-13733-2e fujitsu semiconductor data sheet copyright?2005-2006 fujitsu limited all rights reserved 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90800 series mb90802/802s/803/803s/f804/v800 description the mb90800 series is a general-purpose 16-bit microcon troller that has been developed for high-speed real- time processing required for industrial and office au tomation equipment and proce ss control, etc. the lcd controller of 48 segment four common is built into. instruction set has taken over the sa me at architecture as in the f 2 mc-8l and f 2 mc-16l, and is further enhanced to support high level languages, extend addressing mode , enhanced divide/multiply instructions with sign and enrichment of bit processing. in addition, long word proces sing is now available by introducing a 32-bit accumulator. features ? clock ? built-in pll clock frequency multiplication circuit operating clock (pll clock) : divided-by-2 of oscillation (at oscillation of 6.25 mhz) or 1 to 4 times the oscillation (at os cillation of 6.25 mhz to 25 mhz). minimum instruction execution time of 40.0 ns (at osc illation of 6.25 mhz, four ti mes the pll clock, operation at vcc = 3.3 v) ? the maximum memory space:16 mb 24-bit internal addressing bank addressing (continued) pac k ag e 100 - pin plastic qfp (fpt-100p-m06)
mb90800 series 2 (continued) ? optimized instruction set for controller applications wide choice of data types (bit, byte, word, and long word) wide choice of addressing modes (23 types) high code efficiency enhanced high-precision computi ng with 32-bit accumulator enhanced multiply/divide instructions with sign and the reti instruction ? instruction system compatible with high-l evel language (c language) and multitask employing system stack pointer instruction set has symmetry and barrel shift instructions ? program patch function (2 address pointer) ? 4-byte instruction queue ? interrupt function the priority level can be set to programmable. interrupt function with 32 factors ? data transfer function expanded intelligent i/o service function (ei 2 os): maximum of 16 channels ? low power consumption mode sleep mode (a mode that halts cpu operating clock) time-base timer mode (a mode that oper ates oscillation clock and time-base timer) watch mode (mode in which only the subclock and watch timers operate) stop mode (a mode that stops o scillation clock and sub clock) cpu blocking mode (operating cpu at each set cycle) ? package qfp-100 (fpt-100p-m06:0.65 mm pin pitch) ? process : cmos technology mb90800 series 3 product lineup (continued) part number mb90v800 mb90f804-101/201 mb90802/s mb90803/s type evaluation product flash memory products mask rom products system clock on-chip pll clock multiplication method( 1, 2, 3, 4, 1/2 when pll stops) minimum instruction execution time of 40.0 ns (at oscillation of 6.25 mhz, four times the pll clock) rom capacity no 256 kb 128 kb ram capacity 28 kb 16 kb 2 kb 4 kb cpu functions number of basic instructions : 351 minimum instruction execution time : 40.0 ns/6.25 mhz oscillator (when four times is used : machine clock 25 mhz, power supply voltage : 3.3 v 0.3 v) addressing type : 23 types program patch function : 2 address pointers the maximum memory space : 16mb ports i/o port (cmos) 68 ports (shared with re sources), (70 ports when the subclock is not used) lcd controller/driver segment driver that can drive the lcd panel (liquid crystal display) directly, and common driver 48 seg 4 com 16-bit input/ output timer 16-bit free-run timer 1 channel overflow interrupt output compare (ocu) 2 channels pin input factor: matching of the compare register input capture (icu) 2 channels rewriting a register value upon a pin input (rising edge, falling edge, or both edges) 16-bit reload timer 16-bit reload timer operation (toggle out put, single shot output selectable) the event count function is optional. the event count function is optional. three channels are built in. 16-bit ppg timer output pin 2 ports operating clock frequency : fcp, fcp/22, fcp/24, fcp/26 two channels are built in. timebase timer 1 channel watchdog timer 1 channel timer clock output circuit clock with a frequency of external input clock divided by 16/32/64/128 can be output externally. i 2 c bus i 2 c interface. 1 channel is built-in. 8/10-bit a/d converter 12 channels (input multiplex) the 8-bit resolution or 10-bit resolution can be set. conversion time : 5.9 s (when machine clock 16.8 mhz works). uart full-duplex double buffer asynchronous/synchronous transmit (with start/stop bits) are supported. two channels are built in. extended i/o serial interface two channels are built in. interrupt delay interrupt four channel independence (a/d input and using combinedly) interrupt causes : ?l? ?h? edge/?h? ?l? edge/?l? level/?h? level selectable mb90800 series 4 (continued) part number mb90v800 mb90f804-101/201 mb90803/s dtp/external interrupt 8 channels (the 8 channels includ e with the shared a/d input) interrupt causes : ?l? ?h? edge/?h? ?l? edge/?l? level/?h? level selectable low power consumption mode sleep mode/time-base timer mode/watch mode/stop mode/cpu intermittent mode process cmos operating voltage 2.7 v to 3.6 v mb90800 series 5 pin assignment (top view) (fpt-100p-m06) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p24/seg32 p25/seg33 p26/seg34 p27/seg35 p30/seg36/so3 p31/seg37/sc3 p32/seg38/si3 p33/seg39/tmck p34/seg40/ic0 p35/seg41/ic1 p36/seg42/ocu0 p37seg43/ocu1 x0a/p90 x1a/p91 v cc v ss p40/led0 p41/led1 p42/led2 p43/led3 p44/led4 p45/led5/tot0 p46/led6/tot1 p47/led7/tot2 p50/seg44/tin0 p51/seg45/tin1 p 52/seg46/tin2/ppg0 p53/seg47/ppg1 p54/si0 p55/sc0 p03/seg1 5 p02/seg1 4 p01/seg1 3 p00/seg1 2 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 v ss v cc seg1 seg0 p84/com 3 p83/com 2 com1 com0 v3 v2/p82 v1/p81 v0/p80 rst md0 md1 md2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p56/so0 av cc p57/si1 p76 av ss p60/an0 p61/an1 p62/an2 p63/an3 p64/an4 p65/an5/int0 p66/an6/int1 p67/an7/int2 v ss p70/an8/int3 p71/an9/sc1 p 72/an10/so1 p73/an11/si2 p74/sda/sc2 p75/scl/so2 p23/seg3 1 p22/seg3 0 p21/seg2 9 p20/seg2 8 p17/seg2 7 p16/seg2 6 p15/seg2 5 x0 x1 v ss v cc p14/seg2 4 p13/seg2 3 p12/seg2 2 p11/seg2 1 p10/seg2 0 p07/seg1 9 p06/seg1 8 p05/seg1 7 p04/seg1 6 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mb90800 series 6 pin description (continued) pin no. pin name i/o circuit type* status/function at reset function 92, 93 x0, x1 a oscillation status it is a terminal which connects the oscillator. when connecting an external clock, leave the x1 pin unconnected. 13, 14 x0a, x1a b oscillation status it is 32 khz oscillation pin. (dual-line model) p90, p91 g port input (high-z) general purpose input/output port. (single-line model) 51 md2 m mode pins input pin for selecting operation mode. connect directly to vss. 52, 53 md1, md0 l mode pins input pin for selecting operation mode. connect directly to vcc. 54 rst k reset input external reset input pin. 63, 64, 67 to 76 seg0 to seg11 d lcd seg output a segment output terminal of the lcd controller/ driver. 77 to 84 seg12 to seg19 e port input (high-z) a segment output terminal of the lcd controller/ driver. p00 to p07 general purpose input/output port. 85 to 89, 94 to 96 seg20 to seg27 e a segment output terminal of the lcd controller/ driver. p10 to p17 general purpose input/output port. 97 to 100, 1 to 4 seg28 to seg35 e a segment output terminal of the lcd controller/ driver. p20 to p27 general purpose input/output port. 5 seg36 e a segment output terminal of the lcd controller/ driver. p30 general purpose input/output port. so3 serial data output pin of serial i/o ch.3. valid when serial data output of serial i/o ch.3 is enabled. 6 seg37 e a segment output terminal of the lcd controller/ driver. p31 general purpose input/output port. sc3 serial clock i/o pin of serial i/o ch.3. valid when serial clock output of serial i/o ch.3 is enabled. mb90800 series 7 (continued) pin no. pin name i/o circuit type* status/function at reset function 7 seg38 e port input (high-z) a segment output terminal of the lcd controller/ driver. p32 general purpose input/output port. si3 serial data input pin of serial i/o ch.3. this pin may be used during serial i/o ch.3 in input mode, so it cannot use as other pin function. 8 seg39 e a segment output terminal of the lcd controller/ driver. p33 general purpose input/output port. tmck timer clock output pin. it is effective when perm itting the power output. 9, 10 seg40, seg41 e a segment output terminal of the lcd controller/ driver. p34, p35 general purpose input/output port. ic0, ic1 external trigger input pin of input capture ch.0/ch.1. 11, 12 seg42, seg43 e a segment output terminal of the lcd controller/ driver. p36, p37 general purpose input/output port. ocu0, ocu1 output terminal for the output compares. 17 to 21 led0 to led4 f it is a output terminal for led (i ol = 15 ma). p40 to p44 general purpose input/output port. 22 to 24 led5 to led7 f it is a output terminal for led (i ol = 15 ma). p45 to p47 general purpose input/output port. tot0 to tot2 external event output pin of reload timer ch.0 to ch.2. it is effective when permit ting the external event output. 25, 26 seg44, seg45 e a segment output terminal of the lcd controller/ driver. p50, p51 general purpose input/output port. tin0, tin1 external clock input pin of reload timer ch.0, ch.1. it is effective when permit ting the external clock input. mb90800 series 8 (continued) pin no. pin name i/o circuit type* status/function at reset function 27 seg46 e port input (high-z) a segment output terminal of the lcd controller/ driver. p52 general purpose input/output port. tin2 external clock input pin of reload timer ch.2. it is effective when perm itting the external clock input. ppg0 ppg timer (ch.0) output pin. 28 seg47 e a segment output terminal of the lcd controller/ driver. p53 general purpose input/output port. ppg1 ppg (ch.1) timer output pin. 29 sio g serial data input pin of uart ch.0. this pin may be used during uart ch.0 in receiving mode, so it cannot use as other pin function. p54 general purpose input/output port. 30 sc0 g serial clock input/output pin of uart ch.0. it is effective when permitting the serial clock output of uart ch.0. p55 general purpose input/output port. 31 so0 g serial data output pin of uart ch.0. it is effective when permitting the serial clock output of uart ch.0. p56 general purpose input/output port. 33 si1 g serial data input pin of uart ch.1. this pin may be used during uart ch.1 in receiving mode, so it cannot use as other pin function. p57 general purpose input/output port. 34 p76 g general purpose input/output port. 36 to 40 an0 to an4 i analog input pin ch.0 to ch.4 of a/d converter. enabled when analog input setting is " enabled "(set by ader). p60 to p64 general purpose input/output port. mb90800 series 9 (continued) pin no. pin name i/o circuit type* status/function at reset function 41 to 43 an5 to an7 i analog input (high-z) analog input pin ch.5 to ch.7 of a/d converter. enabled when analog input setting is " enabled ". p65 to p67 general purpose input/output port. int0 to int2 functions as an external interrupt ch.0 to ch.2 input pin. 45 an8 i analog input pin ch.8 of a/d converter. enabled when analog input setting is " enabled ". p70 general purpose input/output port. int3 functions as an external interrupt ch.3 input pin. 46 an9 i port input (high-z) analog input pin ch.9 of a/d converter. enabled when analog input setting is " enabled ". p71 general purpose input/output port. sc1 serial clock input/output pin of uart ch.1. it is effective when permitting the serial clock output of uart ch.1. 47 an10 i analog input pin ch.10 of a/d converter. enabled when analog input setting is " enabled ". p72 general purpose input/output port. so1 serial data output pin of serial i/o ch.1. valid when serial data output of serial i/o ch.1 is enabled. 48 an11 i analog input pin ch.11 of a/d converter. enabled when analog input setting is " enabled ". p73 general purpose input/output port. si2 serial data input pin of serial i/o ch.2. this pin may be used during serial i/o ch.2 in input mode, so it cannot use as other pin function. mb90800 series 10 (continued) * : refer to ? i/o circuit type? for i/o circuit type. pin no. pin name i/o circuit type* status/function at reset function 49 sda h port input (high-z) data input/output pin of i 2 c interface. this pin is enabled when the i 2 c interface is operated. while the i 2 c interface is running, the port must be set for input use. p74 general purpose input/output port. (n-ch open-drain, withstand voltage of 5 v.) sc2 serial clock input pin of serial i/o ch.2. valid when serial clock output of serial i/o ch.2 is enabled. 50 scl h clock input/output pin of i 2 c interface. this pin is enabled when the i 2 c interface is operated. while the i 2 c interface is running, the port must be set for input use. p75 general purpose input/output port. (n-ch open-drain, withstand voltage of 5 v.) so2 serial data output pin of serial i/o ch.2. valid when serial data output of serial i/o ch.2 is enabled. 55 to 57 v0 to v2 j lcd drive power supply input lcd controller/driver. reference power terminals of lcd controller/driver. p80 to p82 general purpose input/output port. 59, 60 com0, com1 d lcd com output a common output terminal of the lcd controller/ driver. 61, 62 p83, p84 e port input (high-z) general purpose input/output port. com2, com3 a common output terminal of the lcd controller/ driver. 32 av cc c power supply a/d converter exclusive power supply input pin. 35 av ss c a/d converter-exclusive gnd power supply pin. 58 v3 j lcd controller/driver reference power terminals of lcd controller/driver. 15, 65, 90 v cc ? these are power supply input pins. 16, 44, 66, 91 v ss ? gnd power supply pin. mb90800 series 11 i/o circuit type (continued) type circuit remarks a oscillation feedback resistance : 1 m ? approx. b low-rate oscillation feedback resistor, approx.10 m ? c analog power supply input protection circuit d lcdc output e cmos output lcdc output hysteresis input (with input interception function at standby) x 1 x 0 p-ch n-ch clock input standby control signal x 1a x 0a p-ch n-ch clock input standby control signal p-ch av p n-ch p-ch n-ch r lcdc output p-ch n-ch r r lcdc output input signal standby control signa l mb90800 series 12 (continued) type circuit remarks f cmos output (heavy-current i ol =15 ma for led drive) hysteresis input (with input interception function at standby) g cmos output cmos hysteresis input (with input interception function at standby) notes : ? the i/o port and internal resources share one output buffer for their outputs. ? the i/o port and internal resources share one input buffer for their input. h hysteresis input (with input interception function at standby) n-ch open drain output i cmos output cmos hysteresis input (with input interception function at standby) analog input (if the bit of analog input enable register = 1, the analog input of a/d converter is enabled.) notes : ? the i/o port and internal resources share one output buffer for their outputs. ? the i/o port and internal resources share one input buffer for their input. p-ch n-ch r input signal standby control signa l p-ch n-ch r input signal standby control sign al n-ch nout r input signal standby control signa l p-ch n-ch r input signal standby control signa l a/d converter analog input mb90800 series 13 (continued) type circuit remarks j cmos output cmos hysteresis input (with input interception function at standby) lcd drive power supply input k cmos hysteresis input with pull-up resistor. l cmos hysteresis input m cmos hysteresis input with pull-down resistor p-ch n-ch r input signal standby control signa l lcd drive power suppl y r r reset input r reset input r r input mb90800 series 14 handling devices 1. preventing latch-up, turning on power supply latch-up may occur on cmos ic under the following conditions: ? if a voltage higher than v cc or lower than v ss is applied to input and output pins, ? a voltage higher than the ra ted voltage is applied between v cc pin and v ss pin. ? if the av cc power supply is turned on before the v cc voltage. ensure that you apply a voltage to the anal og power supply at the same time as v cc or after you turn on the digital power supply (when you perform power-off, turn off the analog power supply first or at the same time as v cc and the digital power supply). when latch-up occurs, power supply current increases rapidly and might thermally damage elements. when using cmos ic, take great care to prevent the occurrence of latch-up. 2. treatment of unused pins if unused input pins are left open, they may cause abno rmal operation or latch-up which may lead to permanent damage to the semiconductor. any such pins should be pulled up or pulled down through resistance of at least 2 k ? . any unused input/output pins should be left open in output status, or if found set to input status, they should be treated in the same way as input pins. any unused output pins should be left open. 3. treatment of a/d converter power supply pins even if the a/d converter is not used , pins should be connected so that av cc = v cc , and av ss = v ss . 4. about the attention when the external clock is used in using an external clock, drive pin x0 only and leave pin x1 open. the example of using an external clock is shown below. please set x0a = gnd and x1a = open without subclock mode. the following figure shows the using sample. x0 x1 open mb90800 serie s x0a x1a open mb90800 serie s mb90800 series 15 5. treatment of power supply pins (v cc /v ss ) in products with multiple v cc or v ss pins, the pins of the same potentia l are internally connected in the device to avoid abnormal operations including latch-up. however, you must connect all power supply pins to external power supply and a ground line to lower the electro-magnet ic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground leve l, and to conform to the total output current rating. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a ceramic capacitor of approximately 0.1 f as a bypass capacitor between v cc and v ss near this device. 6. about crystal oscillators circuit noise near the x0/x1 pins and x0a/x1a pins may cause the device to malfunction. design the printed circuit board so that x0/x1 pins and x0a/x1a pins, the crys tal oscillator (or the ceramic oscillator) and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended to desi gn the pc board artwork with the x0/x1 pins and x0a/x1a pins surrounded by ground plane because stable operation can be expected with such a layout. please ask the crystal maker to evaluate the oscillati onal characteristics of the crystal and this device. 7. caution on operations during pll clock mode on this microcontroller, if in case the crystal oscillator br eaks off or an external reference clock input stops while the pll clock mode is selected, a self-oscillator circuit c ontained in the pll may continue its operation at its self-running frequency. however, fujitsu will not guarant ee results of operations if such failure occurs. 8. stabilization of supply power supply a sudden change in the supply voltage may caus e the device to malfunction even within the v cc supply voltage operating range.therefore, the v cc supply voltage should be stabilized. for reference, the supply voltage should be controlled so that v cc ripple variations (peak- to-peak values ) at commercial frequencies (50 mhz/60 mhz) fall below 10 % of the standard v cc supply voltage and the coefficient of fluctuation does not exceed 0.1 v/ms at instantaneous power switching. 9. note on using the two-subsystem product as one-subsystem product if you are using only one subsystem of the mb90800 series that come in o ne two-subsystem product, use it with x0a = v ss and x1a = open. 10. write to flash ensure that you must write to flash at the operating voltage v cc = 3.0 v to 3.6 v. mb90800 series 16 block diagram f 2 mc-16lx bus x0, x1 x0a*, x1a* rst v0/p80 v1/p81 v2/p82 v3 com0 com1 p83/com2 p84/com3 seg0 to seg11 p00 to p07/ seg12 to seg19 p10 to p17/ seg20 to seg27 p20 to p27/ seg28 to seg35 p30/seg36/so3 p31/seg37/sc3 p32/seg38/si3 p33/seg39/tmck p34/seg40/ic0 p35/seg41/ic1 p36/seg42/ocu0 p37/seg43/ocu1 p40/led0 p41/led1 p42/led2 p43/led3 p44/led4 p45/led5/tot0 p46/led6/tot1 p47/led7/tot2 p50/seg44/tin0 p51/seg45/tin1 p 52/seg46/tin2/ppg0 p53/seg47/ppg1 p54/si0 p55/sc0 p56/so0 p57/si1 12 8 8 8 p60/an0 p61/an1 p62/an2 p63/an3 p64/an4 p65/an5/int0 p66/an6/int1 p67/an7/int2 p70/an8/int3 p71/an9/sc1 p72/an10/so1 p73/an11/si2 p74/sda/sc2 p75/scl/so2 p76 p90* p91* ocu0/1 icu0/1 ppg0/1 uart0/1 ram (2/4/16/28 kb) rom/flash (128/256 kb) i 2 c clock control circuit cpu f 2 mc-16lx core lcd controller/ driver port 8 interrupt controller serial i/o 2/3 prescaler 2/3 free - run timer timer clock output reload timer 0/1/2 prescaler 0/1 8/10 bits ppg a/d converter external interrupt (4 channels) ? : x0a/x1a and p90/p91 can be switched by mask option. notes : ? built-in rom of mb90v800 (evaluation) is not exist. ? the device has built -in ram of 28 kb. port 0 port 1 port 2 port 4 port 3 port 5 port 6 port 7 port 9 mb90800 series 17 memory map memory map of mb90800 series notes : ? when the rom mirror function re gister has been set, the mirror image data at higher addresses ( "ff4000 h to ffffff h " ) of bank ff is visible from the higher addresses ( " 008000 h to 00ffff h " ) of bank 00. ? the rom mirror function is for using the c compiler small model. ? the lower 16-bit addresses of bank ff are equivale nt to those of bank 00. note that because the rom area of bank ff exceeds 32 kb, all data in the rom area cannot be shown in mirror image in bank 00. ? when the c compiler small model is used, the da ta table can be shown as mirror image at " 008000 h to 00ffff h " by storing the data table at " ff8000 h to ffffff h . therefore, data tables in the rom area can be referenced without declaring the far addressing with the pointer. f fffff h 0 0ffff h 008000 h 007917 h 007900 h 000100 h 0 000cf h 0000c0 h 0000bf h 000000 h * : rom is not built into mb90v800. f80000 h is rom decipherment region on the tool side. part number address # 1 address # 2 mb90802 0008ff h fe0000 h mb90803 0010ff h fe0000 h mb90f804 0040ff h fc0000 h mb90v800 0070ff h f80000 h * rom mirror function rom area address #2 address #2 rom mirror area extended i/o area 2 ram area register extended i/o area 1 i/o area mb90800 series 18 f 2 mc - 16l cpu programming model dedicated registers general purpose registers processor status ah al dpr pcb dtb usb ssb adb 8-bit 16-bit 32-bit usp ssp ps pc accumulator user stack pointer system stack pointer processor status program counter direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register r1 r0 r3 r2 r5 r4 r7 r6 rw0 rw1 rw2 rw3 16-bit 000180 h + rp 10 h rw4 rw5 rw6 rw7 rl 0 rl 1 rl 2 rl 3 msb lsb ilm 15 13 p s rp ccr 12 8 70 mb90800 series 19 i/o map (continued) address register abbreviation register read/ write resource name initial value 000000 h pdr0 port 0 data register r/w port 0 xxxxxxxx b 000001 h pdr1 port 1 data register r/w port 1 xxxxxxxx b 000002 h pdr2 port 2 data register r/w port 2 xxxxxxxx b 000003 h pdr3 port 3 data register r/w port 3 xxxxxxxx b 000004 h pdr4 port 4 data register r/w port 4 xxxxxxxx b 000005 h pdr5 port 5 data register r/w port 5 xxxxxxxx b 000006 h pdr6 port 6 data register r/w port 6 xxxxxxxx b 000007 h pdr7 port 7 data register r/w port 7 - xxxxxxx b 000008 h pdr8 port 8 data register r/w port 8 - - - xxxxx b 000009 h pdr9 port 9 data register r/w port 9 - - - - - - xx b 00000a h to 00000f h prohibited 000010 h ddr0 port 0 direction register r/w port 0 0 0 0 0 0 0 0 0 b 000011 h ddr1 port 1 direction register r/w port 1 0 0 0 0 0 0 0 0 b 000012 h ddr2 port 2 direction register r/w port 2 0 0 0 0 0 0 0 0 b 000013 h ddr3 port 3 direction register r/w port 3 0 0 0 0 0 0 0 0 b 000014 h ddr4 port 4 direction register r/w port 4 0 0 0 0 0 0 0 0 b 000015 h ddr5 port 5 direction register r/w port 5 0 0 0 0 0 0 0 0 b 000016 h ddr6 port 6 direction register r/w port 6 0 0 0 0 0 0 0 0 b 000017 h ddr7 port 7 direction register r/w port 7 - 0 0 0 0 0 0 0 b 000018 h ddr8 port 8 direction register r/w port 8 - - - 0 0 0 0 0 b 000019 h ddr9 port 9 direction regist er r/w port 9 - - - - - - 0 0 b 00001a h to 00001d h prohibited 00001e h ader0 analog input enable 0 r/w port 6, a/d 1 1 1 1 1 1 1 1 b 00001f h ader1 analog input enable 1 r/w port 7, a/d - - - - 1 1 1 1 b 000020 h smr0 serial mode register r/w uart0 0 0 0 0 0 - 0 0 b 000021 h scr0 serial control register r/w 0 0 0 0 0 1 0 0 b 000022 h s1dr0/ sodr0 serial input/output register r/w xxxxxxxx b 000023 h ssr0 serial data register r/w 0 0 0 0 10 0 0 b 000024 h prohibited 000025 h cdcr0 communication prescaler control register r/w prescaler 0 0 0 - - 0 0 0 0 b 000026 h , 000027 h prohibited mb90800 series 20 (continued) address register abbreviation register read/ write resource name initial value 000028 h smr1 serial mode register r/w uart1 0 0 0 0 0 - 0 0 b 000029 h scr1 serial control register r/w, w 0 0 0 0 0 1 0 0 b 00002a h sidr1/ sodr1 serial input/output register r/w xxxxxxxx b 00002b h ssr1 serial data register r/w, r 0 0 0 0 1 0 0 0 b 00002c h prohibited 00002d h cdcr1 communication prescaler control register r/w prescaler 1 0 0 - - 0 0 0 0 b 00002e h prohibited 00002f h 000030 h enir interrupt/dtp enable r/w external interrupt - - - - 0 0 0 0 b 000031 h eirr interrupt/dtp source r/w - - - - xxxx b 000032 h elvr request level set register r/w 0 0 0 0 0 0 0 0 b 000033 h prohibited 000034 h adcs0 control status register (lower) r/w a/d converter 0 0 - - - - - - b 000035 h adcs1 control status register (upper) w, r/w 0 0 0 0 0 0 0 0 b 000036 h adcr0 data register (lower) r xxxxxxxx b 000037 h adcr1 data register (upper) r, w 0 0 1 0 1 - xx b 000038 h prohibited 000039 h admr a/d conversion channel set regist er r/w a/d converter 0 0 0 0 0 0 0 0 b 00003a h cpclr compare clear register r/w 16-bit free-run timer xxxxxxxx b 00003b h xxxxxxxx b 00003c h tcdt timer counter data register r/w 0 0 0 0 0 0 0 0 b 00003d h 0 0 0 0 0 0 0 0 b 00003e h tccsl timer counter control/status register (lower) r/w 0 0 0 0 0 0 0 0 b 00003f h tccsh timer counter control/status register (upper) r/w 0 - - 0 0 0 0 0 b 000040 h to 000043 h prohibited 000044 h ipcp0 input capture data register 0 r input capture 0/1 xxxxxxxx b 000045 h xxxxxxxx b 000046 h ipcp1 input capture data register 1 xxxxxxxx b 000047 h xxxxxxxx b 000048 h ics01 control status register r/w 0 0 0 0 0 0 0 0 b 000049 h prohibited 00004a h occp0 compare register 0 r/w output compare 0 0 0 0 0 0 0 0 0 b 00004b h 0 0 0 0 0 0 0 0 b 00004c h occp1 compare register 1 r/w output compare 1 0 0 0 0 0 0 0 0 b 00004d h 0 0 0 0 0 0 0 0 b mb90800 series 21 (continued) address register abbreviation register read/ write resource name initial value 00004e h ocsl control register (lower) r/w output compare 0/1 0 0 0 0 - - 0 0 b 00004f h ocsh control register (upper) r/w - - - 0 0 0 0 0 b 000050 h tmcsr0l timer control status register (lower) r/w 16-bit reload timer 0 0 0 0 0 0 0 0 0 b 000051 h tmcsr0h timer control status register (upper) r/w - - - - 0 0 0 0 b 000052 h tmr0/ tmrlr0 16-bit timer register/reload register r/w xxxxxxxx b 000053 h xxxxxxxx b 000054 h tmcsr1l timer control status register (lower) r/w 16-bit reload timer 1 0 0 0 0 0 0 0 0 b 000055 h tmcsr1h timer control status register (upper) r/w - - - - 0 0 0 0 b 000056 h tmr1/ tmrlr1 16-bit timer register/reload register r/w xxxxxxxx b 000057 h xxxxxxxx b 000058 h tmcsr2l timer control status register (lower) r/w 16-bit reload timer 2 0 0 0 0 0 0 0 0 b 000059 h tmcsr2h timer control status regi ster (upper) r/w - - - - 0 0 0 0 b 00005a h tmr2/ tmrlr2 16-bit timer register/reload register r/w xxxxxxxx b 00005b h xxxxxxxx b 00005c h lcrl lcd control register (lower) r/w lcd controller/ driver 0 0 0 1 0 0 0 0 b 00005d h lcrh lcd control register (upper) r/w 0 0 0 0 0 0 0 0 b 00005e h lcrr lcd range register r/w 0 0 0 0 0 0 0 0 b 00005f h prohibited 000060 h smcs0 serial mode control status register r, r/w sio (extended serial i/o) 0 0 0 0 0 0 1 0 b 000061 h r/w - - - - 0 0 0 0 b 000062 h sdr0 serial data register r/w xxxxxxxx b 000063 h sdcr0 communication prescaler control register r/w communication prescaler (sio) 0 - - - 0 0 0 0 b 000064 h smcs1 serial mode control status register r, r/w sio (extended serial i/o) 0 0 0 0 0 0 1 0 b 000065 h r/w - - - - 0 0 0 0 b 000066 h sdr1 serial data register r/w xxxxxxxx b 000067 h sdcr1 communication prescaler control register r/w communication prescaler (sio) 0 - - - 0 0 0 0 b 000068 h prohibited 000069 h 00006a h ibsr i 2 c status register r i 2 c 0 0 0 0 0 0 0 0 b 00006b h ibcr i 2 c control register r/w 0 0 0 0 0 0 0 0 b 00006c h iccr i 2 c clock selection register r/w xx0xxxxx b 00006d h iadr i 2 c address register r/w xxxxxxxx b 00006e h idar i 2 c data register r/w xxxxxxxx b 00006f h romm rom mirror function select register r/w, w rom mirror xxxxxxx1 b mb90800 series 22 (continued) address register abbreviation register read/ write resource name initial value 000070 h pdcrl0 pdcrl0/pdcrh0 ppg down counter register r 16-bit ppg0 1 1 1 1 1 1 1 1 b 000071 h pdcrh0 1 1 1 1 1 1 1 1 b 000072 h pcsrl0 pcsrl0/pcsrh0 ppg cycle set register w xxxxxxxx b 000073 h pcsrh0 xxxxxxxx b 000074 h pdutl0 pdutl0/pduth0 ppg duty setting register w xxxxxxxx b 000075 h pduth0 xxxxxxxx b 000076 h pcntl0 pcntl0/pcnth0 ppg control status register r/w - - 0 0 0 0 0 0 b 000077 h pcnth0 0 0 0 0 0 0 0 - b 000078 h pdcrl1 pdcrl1/pdcrh1 ppg down counter register r 16-bit ppg1 1 1 1 1 1 1 1 1 b 000079 h pdcrh1 1 1 1 1 1 1 1 1 b 00007a h pcsrl1 pcsrl1/pcsrh1 ppg cycle set register w xxxxxxxx b 00007b h pcsrh1 xxxxxxxx b 00007c h pdutl1 pdutl1/pduth1 ppg duty setting register w xxxxxxxx b 00007d h pduth1 xxxxxxxx b 00007e h pcntl1 pcntl1/pcnth1 ppg control status register r/w - - 0 0 0 0 0 0 b 00007f h pcnth1 0 0 0 0 0 0 0 - b 000080 h to 000095 h (reserved) 000096 h prohibited 000097 h (reserved) 000098 h to 00009d h prohibited 00009e h pacsr rom correction control register r/w rom correction 0 0 0 0 0 0 0 0 b 00009f h dirr delayed interrupt source generated/ release register r/w delayed interrupt - - - - - - - 0 b 0000a0 h lpmcr low power consumption mode control register r/w, w low power consumption control circuit 0 0 0 1 1 0 0 0 b 0000a1 h ckscr clock selector register r/w, r 1 1 1 1 1 1 0 0 b 0000a2 h to 0000a7 h prohibited 0000a8 h wdtc watchdog timer control r, w watchdog timer xxxxx 1 1 1 b 0000a9 h tbtc time-base timer control register r/ w, w time-base timer 1 - - 0 0 1 0 0 b 0000aa h wtc watch timer control register r/w, r watch timer (sub clock) 1 x0 1 1 0 0 0 b 0000ab h to 0000ad h prohibited mb90800 series 23 (continued) read/write initial values address register abbreviation register read/ write resource name initial value 0000ae h fmcs flash control register r/w flash i/f 0 0 0 x 0 0 0 0 b 0000af h tmcs timer clock output control register r/w timer clock divide xxxxx 0 0 0 b 0000b0 h icr00 interrupt control register 00 r/w, w, r interrupt controller 0 0 0 0 0 1 1 1 b 0000b1 h icr01 interrupt control register 01 r/w, w, r 0 0 0 0 0 1 1 1 b 0000b2 h icr02 interrupt control register 02 r/w, w, r 0 0 0 0 0 1 1 1 b 0000b3 h icr03 interrupt control register 03 r/w, w, r 0 0 0 0 0 1 1 1 b 0000b4 h icr04 interrupt control register 04 r/w, w, r 0 0 0 0 0 1 1 1 b 0000b5 h icr05 interrupt control register 05 r/w, w, r 0 0 0 0 0 1 1 1 b 0000b6 h icr06 interrupt control register 06 r/w, w, r 0 0 0 0 0 1 1 1 b 0000b7 h icr07 interrupt control register 07 r/w, w, r 0 0 0 0 0 1 1 1 b 0000b8 h icr08 interrupt control register 08 r/w, w, r 0 0 0 0 0 1 1 1 b 0000b9 h icr09 interrupt control register 09 r/w, w, r 0 0 0 0 0 1 1 1 b 0000ba h icr10 interrupt control register 10 r/w, w, r 0 0 0 0 0 1 1 1 b 0000bb h icr11 interrupt control register 11 r/w, w, r 0 0 0 0 0 1 1 1 b 0000bc h icr12 interrupt control register 12 r/w, w, r 0 0 0 0 0 1 1 1 b 0000bd h icr13 interrupt control register 13 r/w, w, r 0 0 0 0 0 1 1 1 b 0000be h icr14 interrupt control register 14 r/w, w, r 0 0 0 0 0 1 1 1 b 0000bf h icr15 interrupt control register 15 r/w, w, r 0 0 0 0 0 1 1 1 b 001ff0 h padr0 program address detection register 0 r/w address matching detection function xxxxxxxx b 001ff1 h xxxxxxxx b 001ff2 h xxxxxxxx b 001ff3 h padr1 program address detection register 1 r/w xxxxxxxx b 001ff4 h xxxxxxxx b 001ff5 h xxxxxxxx b 007900 h to 007917 h vram lcd display ram r/w lcd controller/ driver xxxxxxxx b r/w : readable and writable r : read only w : write only 0 : initial value is ?0?. 1 : initial value is ?1?. x : initial value is indeterminate. - : unused bit mb90800 series 24 interrupt sources, interrupt vectors and interrupt control registers : available : unavailable : available el 2 os function is provided. : available when a cause of interru pt sharing a same icr is not used. * : when interrupts of the same level are output at the same time, the in terrupt with the smallest interrupt vector number has the priority. ? for a resource that has two interr upt causes in the same interrupt control register (icr), use of ei 2 os is enabled, ei 2 os is started upon detection of one of the interrupt causes. as interrupts other than the start cause are masked during ei 2 os start, masking one of the interrupt causes is recommended when using ei 2 os. ? for a resource that has two interrupt causes in the same interrupt control register (icr), the interrupt flag is cleared by an ei 2 os interrupt clear signal. interrupt source ei 2 os readiness interrupt vector interrupt control register priority number* address icr address reset #08 08 h ffffdc h ?? high int 9 instruction #09 09 h ffffd8 h ?? exceptional treatment #10 0a h ffffd4 h ?? dtp/external interrupt ch.0 #11 0b h ffffd0 h icr00 0000b0 h dtp/external interrupt ch.1 #13 0d h ffffc8 h icr01 0000b1 h serial i/o ch.2 #15 0f h ffffc0 h icr02 0000b2 h dtp/external interrupt ch.2/ch.3 #16 10 h ffffbc h serial i/o ch.3 #17 11 h ffffb8 h icr03 0000b3 h 16-bit free-run timer #18 12 h ffffb4 h watch timer #19 13 h ffffb0 h icr04 0000b4 h 16-bit reload timer ch.2 #21 15 h ffffa8 h icr05 0000b5 h 16-bit reload timer ch.0 #23 17 h ffffa0 h icr06 0000b6 h 16-bit reload timer ch.1 #24 18 h ffff9c h input capture ch.0 #25 19 h ffff98 h icr07 0000b7 h input capture ch.1 #26 1a h ffff94 h ppg timer ch.0 counter-borrow #27 1b h ffff90 h icr08 0000b8 h output compare match #29 1d h ffff88 h icr09 0000b9 h ppg timer ch.1 counter-borrow #31 1f h ffff80 h icr10 0000ba h time-base timer #33 21 h ffff78 h icr11 0000bb h uart0 reception end #35 23 h ffff70 h icr12 0000bc h uart0 transmission end #36 24 h ffff6c h a/d converter conversion termination #37 25 h ffff68 h icr13 0000bd h i 2 c interface #38 26 h ffff64 h uart1 : reception #39 27 h ffff60 h icr14 0000be h uart1 : transmission #40 28 h ffff5c h flash memory status #41 29 h ffff58 h icr15 0000bf h delayed interrupt output module #42 2a h ffff54 h low mb90800 series 25 peripheral resources 1. i/o port the i/o ports function to output data from the cpu to i/o pins by setting their port data register (pdr) and send signals input to i/o pins to the cpu. in addition, the port can randomly set the direction of the input/output of the port in bit by the port direction register (ddr). the mb90800 series has 68 (70 ports when the subclock is not used) input/output pins. port0 to port8 (port0 to port9 when product without the subclo ck is used) are input/output port. (1) port data register * : r/w access to i/o ports is a bit different in behavior from r/w access to memory as follows ? input mode when reading : read the corresponding pin level. when writing : write into the latch for the output. ? output mode when reading : read the value of the data register latch. when writing : write into the corresponding pin. - : unused pdr0 initial value access address : 000000 h indeterminate r/w* pdr1 address : 000001 h indeterminate r/w* pdr2 address : 000002 h indeterminate r/w* pdr3 address : 000003 h indeterminate r/w* pdr4 address : 000004 h indeterminate r/w* pdr5 address : 000005 h indeterminate r/w* pdr6 address : 000006 h indeterminate r/w* pdr7 address : 000007 h indeterminate r/w* pdr8 address : 000008 h indeterminate r/w* pdr9 address : 000009 h indeterminate r/w* 7654 321 0 p06 p07 p05 p04 p03 p02 p01 p00 15 14 13 12 11 10 9 8 p16 p17 p15 p14 p13 p12 p11 p10 7654 321 0 p26 p27 p25 p24 p23 p22 p21 p20 15 14 13 12 11 10 9 8 p36 p37 p35 p34 p33 p32 p31 p30 7654 321 0 p46 p47 p45 p44 p43 p42 p41 p40 15 14 13 12 11 10 9 8 p56 p57 p55 p54 p53 p52 p51 p50 7654 321 0 p66 p65 p64 p63 p62 p61 p60 p67 15 14 13 12 11 10 9 8 p76 p75 p74 p73 p72 p71 p70 ? 7654 321 0 p84 p83 p82 p81 p80 ? ? ? 15 14 13 12 11 10 9 8 p91 p90 ? ? ? ? ? ? mb90800 series 26 (2) port direction register when each terminal functions as a por t, each correspondent pin are controlled by the port direction register to following; 0 : input mode 1 : output mode this bit becomes ?0? after a reset. note : when accessing this register by using the instructio n of the read modify write system (instructions such as bit set) is mode, the bit targeted by an instruction becomes the defined value. ho wever, the content of the output register set to input with the other changes to input value of the pi n at that time. therefore, be sure to write an expected value into pdr firstly, and then se t ddr and finally change to the output when changing the input pin to the output pin is made. - : unused ddr0 initial value access address : 000010 h 00000000 b r/w ddr1 address : 000011 h 00000000 b r/w ddr2 address : 000012 h 00000000 b r/w ddr3 address : 000013 h 00000000 b r/w ddr4 address : 000014 h 00000000 b r/w ddr5 address : 000015 h 00000000 b r/w ddr6 address : 000016 h 00000000 b r/w ddr7 address : 000017 h - 0000000 b r/w ddr8 address : 000018 h - - - 00000 b r/w ddr9 address : 000019 h - - - - - - 00 b r/w 7654 321 0 d06 d07 d05 d04 d03 d02 d01 d 00 15 14 13 12 11 10 9 8 d16 d17 d15 d14 d13 d12 d11 d10 7654 321 0 d26 d27 d25 d24 d23 d22 d21 d20 15 14 13 12 11 10 9 8 d36 d37 d35 d34 d33 d32 d31 d30 7654 321 0 d46 d47 d45 d44 d43 d42 d41 d40 15 14 13 12 11 10 9 8 d56 d57 d55 d54 d53 d52 d51 d50 7654 321 0 d66 d67 d65 d64 d63 d62 d61 d60 15 14 13 12 11 10 9 8 d75 d74 d73 d72 d71 d70 d76 ? 7654 321 0 d84 d83 d82 d81 d80 ? ? ? 15 14 13 12 11 10 9 8 d91 d90 ? ? ? ? ? ? mb90800 series 27 (3) analog input enable register each pin of port 6 is controlled by t he analog input enable register as follow. 0 : port input/output mode. 1 : analog input mode.this bit becomes ?1? after a reset. - : unused ader0 initial value access address : 00001e h 11111111 b r/w ader1 address : 00001f h - - - - 1111 b r/w 7654 321 0 ade3 ade2 ade1 ade0 ade7 ade6 ade5 ade4 15 14 13 12 11 10 9 8 ade11 ade10 ade9 ade8 ???? mb90800 series 28 2. uart uart is a serial i/o port for asynchronous (start-stop synchronization) communication or clk synchronous communications. with full-duplex double buffer clock asynchronous (start-stop synchronization) , clk synchronous communications (no start-bit/stop-bit) can be used. supports multi-processor mode built-in dedicated baud rate generator asynchronous : 120192/60096/30048/ 15024/781.25 k/390.625 kbps clk synchronous : 25 m/12.5 m/6.25 m/3.125 m/1.5627 m/781.25 kbps variable baud rate can be set by an external clock. 7-bits data length (only asynchr onous normal mode) /8-bits length master/slave type communication function (at multip rocessor mode) : the communication between one (mas- ter) to n (slave) can be operating. error detection functions(parity, framing, overrun) transmission signal format is nrz mb90800 series 29 (1) register list serial mode register (smr0, smr1) serial control register(scr0, scr1) serial input/output register (sidr0, sidr1/sodr0, sodr1) serial data register (ssr0, ssr1) communication prescaler cont rol register (cdcr0, cdcr1) - : unused initial value address : 000020 h 000028 h 00000 - 00 b read/write initial value address : 000021 h 000029 h 00000100 b read/write initial value address : 000022 h 00002a h xxxxxxxx b read/write initial value address : 000023 h 00002b h 00001000 b read/write initial value address : 000025 h 00002d h 00 - - 0000 b read/write smr ? cdcr scr 15 0 sidr (r)/sodr (w) ssr 87 8-bit 8-bit r/w r/w r/w r/w ? r/w r/w 7654 3210 md0 r/w md1 cs2 cs1 cs0 ? scke soe r/w r/w r/w r/w w r/w r/w 15 14 13 12 11 10 9 8 p r/w pen sbl cl a/d rec rxe txe r/w r/w r/w r/w r/w r/w r/w 7654 3210 d6 r/w d7 d5 d4 d3 d2 d1 d0 r r r r r/w r/w r/w 15 14 13 12 11 10 9 8 ore r pe fre rdrf tdre bds rie tie r/w ?? r/w r/w r/w r/w 15 14 13 12 11 10 9 8 urst r/w md ?? div2 div1 div0 reserved mb90800 series 30 (2) block diagram md1 md0 cs2 cs1 cs0 scke soe pen p sbl cl a/d rec rex txe pe ore fre rdrf tdre bds rie tie f 2 mc-16lx bus sidr sodr control signal 16-bit reload timer 0 pin clock selection circuit receive status decision circuit reception error occurrence signal for ei 2 os (to cpu) reception clock reception control circuit start bit detection circuit reception bit counter reception parity counter rx shifter reception control circuit transmission clock rx interrupt (to cpu) tx interrupt (to cpu) transmission control circuit transmission start circuit transmission bit counter transmission parity counter tx shifter start transmission smr register control signal scr register ssr register special-purpose baud-rate generator pin pin mb90800 series 31 3. i 2 c interface i 2 c interface is the serial input/output port that support inter ic bus and functions as the master/slave device on the i 2 c bus. mb90800 series have 1 channel of the built-in i 2 c interface. it has the features of i 2 c interface below. master/slave sending and receiving arbitration function clock synchronization function slave address and general ca ll address detection function detecting transmitting direction function repeat generating and detecting f unction of the start conditions bus error detection function the forwarding rate can be supported to 100 kbps. (1) register list i 2 c status register (ibsr) i 2 c control register (ibcr) i 2 c clock control register (iccr) i 2 c data register(idar) i 2 c address register (iadr) - : unused initial value address :00006a h 00000000 b read/write initial value address :00006b h 00000000 b read/write initial value address :00006c h xx0xxxxx b read/write initial value address :00006e h xxxxxxxx b read/write initial value address :00006d h xxxxxxxx b read/write 7654 321 0 rsc bb al lrb trx aas gca fbt r rrrrrrr 15 14 13 12 11 10 9 8 beie ber scc mss ack gcaa inte int r/w r/w r/w r/w r/w r/w r/w r/w 7654 321 0 ? ? en cs4 cs3 cs2 cs1 cs0 ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 d6 r/w d7 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w 7654 3210 a6 ? ? a5 a4 a3 a2 a1 a0 mb90800 series 32 (2) block diagram iccr 5 2 4 8 16 32 64 128 256 sync first byte 678 en iccr cs4 cs3 ibsr last bit irq idar iadr sc l sd a bb rsc lrb trx fbt al ibcr ber beie inte int ibcr scc mss ack gcaa ibsr aas gca cs2 cs1 cs0 internal data bus i 2 c enable clock divide 1 machine clock clock selector 1 clock divide 2 clock selector 2 generating shift clock change timing of shift clock edge bus busy repeat start transfer/ reception start ? stop condition detection arbitration lost detection interrupt request start master ack enable gc-ack enable start ? stop condition detection slave address compare slave global call error end mb90800 series 33 4. extended i/o serial interface the extended i/o serial interface is a serial i/o inte rface that can transfer data through the adoption of 8-bit 2 channels configured clock synchronization scheme. the ex tended i/o serial interface also has two alternatives in data transfer called lsb first and msb first. the serial i/o interface operates in two modes: (1) register list internal shift clock mode : transfer data in sync with the internal clock. external shift clock mode : transfers data in sync with the clock input through an external pin (sck) . in this mode, transfer operation performed by the cpu instruction is also available by operating the general-use port sharing an external pin (sck) . serial mode control status register(smcs0, smcs1) serial data register (sdr0, sdr1) communication prescaler control register (sdcr0, sdcr1) - : unused initial value address : 000060 h 000064 h 00000010 b read/write address : 000061 h 000065 h ----0000 b read/write address : 000062 h 000066 h xxxxxxxx b read/write address : 000063 h 000067 h 0---0000 b read/write 15 14 13 12 11 10 9 8 smd1 smd2 smd0 sie sir busy stop strt r/w r/w r/w r/w r/w r r/w r/w 7654 321 0 ? ??? mode bds soe scoe r/w r/w r/w r/w ???? 7654 321 0 d6 d7 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w ??? r/w r/w r/w r/w 15 14 13 12 11 10 9 8 ? r/w md ?? div2 div1 div0 reserved mb90800 series 34 (2) block diagram si2, si3 s o2, so3 sc2, sc3 smd2 smd1 smd0 sie sir busy stop strt mode bds 21 0 soe scoe (msb fast) d0 to d7 (lsb fast) d7 to d0 sdr (serial data register) internal clock internal data bus transfer direction selection read write control circuit shift clock counter interrupt request internal data bus initial value mb90800 series 35 5. 8/10-bit a/d converter the feature of 8/10-bit a/d converter is shown as follows. conversion time : 3.1 s minimum per 1 channel (78 machine cycle/at machine clock 25 mhz/including the sampling time) sampling time : 2.0 s minimum per 1channel (50 machine cycle/at machine clock 25 mhz) uses rc-type successive approximation conversion method with a sample & hold circuit 8-bit resolution or 10-bit resolution can be select. 12 channel program-selectable analog inputs. single conversion mode : convert specified 1 channel scan conversion mode : continuous plural c hannels (maximum 12 channels can be programmed) are converted. continuous conversion mode : selected channel converted continuously. stop conversion time : perform conversion for one channel, then pause it to wait for the next activation trigger (synchronizes the conversion start timing) ei 2 os can be activated by outputting the inte rrupt request when the a/d conversion completes. if the a/d conversion is performed under the conditio n of the interrupt enable, the converting data will be protected. selectable conversion activation trigger : software, or reload timer (rising edge) (1) register list adcs1, adcs0 (control status register) adcr1, adcr0 (data register) - : unused adcs0 initial value address : 000034 h 00 - - - - - - b read/write adcs1 bit initial value address : 000035 h 00000000 b read/write adcr0 bit initial value address : 000036 h xxxxxxxx b read/write adcr1 bit initial value address : 000037 h 00101 - xx b read/write r/w ?? ? ? ? ? 7654 3210 md0 r/w md1 ???? ?? r/w r/w r/w r/w r/w w r/w 15 14 13 12 11 10 9 8 int r/w busy inte paus sts1 sts0 strt reserved rrrrrrr 7654 3210 d6 r d7 d5 d4 d3 d2 d1 d0 wwww ? rr 15 14 13 12 11 10 9 8 st1 w s10 st0 ct1 ct0 ? d9 d8 mb90800 series 36 (2) block diagram mp a n0 a n1 a n2 a n3 a n4 a n5 a n6 a n7 a n8 a n9 a n10 a n11 adcr0, adcr1 adcs0, adcs1, av cc avr av ss admr input circuit d/a converter sequential compare register data register adcs0 a/d control status register 0 (lower) adcs1 a/d control status register 1 (upper) prescaler operation clock timer start-up decoder comparator sample & hold circuit 16-bit reload timer data bus a/d conversion channel set register mb90800 series 37 6. 16 bits ppg the ppg timer consists of the following: prescaler 16-bit down-counter: 1 16-bit data register with a cycle setting buffer 16-bit compare register with a duty setting buffer pin control unit the ppg timer can output pulses synchronized to the software trigger. the output pulse can be changed to any cycle and duty freely by updating the pc srl, pcsrh/pdutl, pduth registers. pwm function the ppg timer can output pulses programmably by updat ing the pcsr and pdvt registers described above in synchronization to the trigger. can also be used as a d/a converter by an external circuit. single shot function by detecting an edge of the trigger input, a single pulse can be output. 16-bit down counter the counter operation clock comes fr om eight kinds optional. there are eight kinds of internal clocks. ( , 2, 4, 8, 16, 32, 64, 128) : machine clock the counter can be in itialized to " ffff h " at a reset or counter borrow. interrupt request the ppg timer generates an interrupt request when : timer start-up counter borrow occurrence (cycle match) duty match occurrence mb90800 series 38 (1) register list pcnth (pcnth0/pcnth1 control status register) pcntl (pcntl0/pcntl1 control status register) pdcrh (pdcrh0/pdcrh1 ppg down counter register) pdcrl (pdcrl0/pdcrl1 ppg down counter register) pcsrh (pcsrh0/pcsrh1 ppg cycle set register) pcsrl (pcsrl0/pcsrl1 ppg cycle set register) pduth (pduth0/pduth1 ppg duty set register) pdutl (pdutl0/pdutl1 ppg duty set register) - : unused 000077 h 00007f h initial value 0000000x b read/write 000076 h 00007e h initial value - - 000000 b read/write 000071 h 000079 h initial value 11111111 b read/write 000070 h 000078 h initial value 11111111 b read/write 000073 h 00007b h initial value xxxxxxxx b read/write 000072 h 00007a h initial value xxxxxxxx b read/write 000075 h 00007d h initial value xxxxxxxx b read/write 000074 h 00007c h initial value xxxxxxxx b read/write r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 stgr r/w cnte mdse rtrg csk2 csk1 csk0 pgms ? r/w r/w r/w r/w r/w r/w 7654 3210 ? ? ? iren irqf irs1 irs0 poen osel rrrrrrr 15 14 13 12 11 10 9 8 dc14 r dc15 dc13 dc12 dc11 dc10 dc09 dc08 rrrrrrr 7654 3210 dc06 r dc07 dc05 dc04 dc03 dc02 dc01 dc00 wwwwww w 15 14 13 12 11 10 9 8 cs14 w cs15 cs13 cs12 cs11 cs10 cs09 cs08 wwwwwww 7654 3210 cs06 w cs07 cs05 cs04 cs03 cs02 cs01 cs00 wwwwwww 15 14 13 12 11 10 9 8 du14 w du15 du13 du12 du11 du10 du09 du08 wwwwwww 7654 3210 du06 w du07 du05 du04 du03 du02 du01 du00 mb90800 series 39 (2) block diagram ? 16-bit ppg ch.0/ch.1 block diagram 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128 pcsr ck pdut cmp sq r prescaler pcnt 16-bit down counter load borrow start machine clock enable soft trigger ppg mask ppg output reverse bit interrupt interrupt select mb90800 series 40 7. delay interrupt generator module the delayed interrupt generation module outputs an interr upt request for task switching. the hardware interrupt request can be generated by software. (1) register list (2) block diagram delayed interrupt/release register(dirr) - : unused dirr initial value address : 00009f h - - - - - - - 0 b read/write 15 14 13 12 11 10 9 8 ??????? r/w ? ? ????? r0 f 2 mc-16lx bus delay interruption factor generation/ release decoder factor latch mb90800 series 41 8. dtp/external interrupt dtp (data transfer peripheral)/external interrupt circui t detects the interrupt reques t input from the external interrupt input terminal, and outputs the interrupt request. (1) register list (2) block diagram interrupt/dtp enable register (enir) interrupt/dtp source register (eirr) request level setting register (elvr) - : unused enir initial value address : 000030 h - - - - 0000 b read/write eirr initial value address : 000031 h - - - - xxxx b read/write initial value address : 000032 h 00000000 b read/write 7654 3210 ???? r/w r/w r/w r/w ? ??? en3 en2 en1 en0 15 14 13 12 11 10 9 8 ???? r/w r/w r/w r/w ? ??? er3 er2 er1 er0 7654 321 0 r/w r/w r/w r/w r/w r/w r/w r/w la3 lb3 lb2 la2 lb1 la1 lb0 la0 4 4 4 8 4 f 2 mc-16lx bus interrupt/dtp enable register gate source f/f edge detection circuit request input interrupt/dtp source register request level setting register mb90800 series 42 9. 16-bit input/output timer the 16-bit i/o timer consists of one 16- bit free-run timer, two output compare and two input capture. this function enables six independent waveforms to be output based on the 16-bit free-run timer, and input pulse widths and external clock frequencies to be measured. ? register list 16-bit free-run timer 16-bit output compare 16-bit input capture cpclr 15 0 00003b h /00003a h 0 0003d h /00003c h 00003f h /00003e h tcdt tccsl tccsh compare clear register timer counter data register timer counter control/status register occp0, occp1 15 0 ocsl ocsh 0 0004a h /00004b h / 00004c h /00004d h 00004f h /00004e h compare register control status register ipcp0, ipcp1 15 0 ics01 0 00044 h /000045 h / 000046 h /000047 h 000048 h input capture data register control status register mb90800 series 43 ? block diagram tq tq ocu 0 ocu 1 ic0 ic1 bus 16-bit free-run timer output compare 0 output compare 1 control logic interrupt 16-bit timer compare register 0 clear compare register 1 capture register 0 capture register 1 to each block edge select edge select input capture 0 input capture 1 mb90800 series 44 (1) 16-bit free-run timer the 16-bit free-run timer consists of a 16-bi t up-down counter and control status register. counter value of 16-bit free-run timer is available as base timer for input c apture and output compare. clock for the counter operation can be selected from eight types. the counter overflow interruption can be generated. setting the mode enables initialization of the counter through compare-match operat ion with the value of the compare clear register in the output compar e and that of the free-run timer counter. ? register list compare clear register (cpclr) timer counter data register (tcdt) timer counter control/status register (tccs) - : unused initial value 00003b h xxxxxxxx b read/write initial value 00003a h xxxxxxxx b read/write initial value 00003d h 00000000 b read/write initial value 00003c h 00000000 b read/write initial value 00003f h 0--00000 b read/write initial value 00003e h 00000000 b read/write 15 14 13 12 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w cl14 cl15 cl13 cl12 cl11 cl10 cl09 cl08 7654 321 0 r/w r/w r/w r/w r/w r/w r/w r/w cl06 cl07 cl05 cl04 cl03 cl02 cl01 cl00 15 14 13 12 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w t14 t15 t13 t12 t11 t10 t09 t08 7654 321 0 r/w r/w r/w r/w r/w r/w r/w r/w t06 t07 t05 t04 t03 t02 t01 t00 15 14 13 12 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w ? ecke ? msi2 msi1 msi0 iclr icre 7654 321 0 r/w r/w r/w r/w r/w r/w r/w r/w ivfe ivf stop mode sclr clk2 clk1 clk0 mb90800 series 45 ? block diagram ivf ivfe stop mode sclr clk1 clk0 iclr msi2 to msi0 icre clk2 bus interrupt request 16-bit free-run timer count value output t15 to t00 divider clock interrupt request 16-bit compare clear register compare circuit mb90800 series 46 (2) output compare the output compare consists of 16-bit compare registers, compare output pin part and a control register. it can reverse the output level for the pin and at the same ti me, generate an interrupt when the 16-bit free-run timer value matches a value set in one of the 16 -bit compare registers of this module. it has a total of six compare registers that can operate independently. in addition, t he output can be set to be controlled by using two compare registers. an interrupt can be set by a comparing match. ? register list compare register (occp0, occp1) control register (ocsh) control register (ocsl) - : unused initial value 00004b h 00004d h 00000000 b read/write initial value 00004a h 00004c h 00000000 b read/write initial value 00004f h ---00000 b read/write initial value 00004e h 0000--00 b read/write 15 14 13 12 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w op14 op15 op13 op12 op11 op10 op09 op08 7654 321 0 r/w r/w r/w r/w r/w r/w r/w r/w op06 op07 op05 op04 op03 op02 op01 c00 15 14 13 12 11 10 9 8 ??? r/w r/w r/w r/w r/w ? ?? cmod ote1 ote0 otd1 otd0 7654 321 0 r/w r/w r/w r/w ?? r/w r/w iop0 iop1 ioe1 ioe0 ?? cst1 cst0 mb90800 series 47 ? block diagram icp1 icp0 ice0 ice0 tq tq cmod ote1 ote0 bus 16-bit timer counter value (t15 to t00) compare control compare register 0 16-bit timer counter value (t15 to t00) compare control compare register 1 control logic each control blocks #29 #29 interrupt mb90800 series 48 (3) input capture the input capture consists of inpu t capture and control registers. ea ch input capture has its corresponding external input pin. this module has a function that detects a rising edge, fa lling edge or both edges and holds a value of the 16- bit free-run timer in a register at th e time of detection. it can also gene rate an interrupt when detecting an edge. the detection edge of an external input can be selected from among three types. rising edge/falling edge/ both edges. it can generate an interrupt when it detect s the valid edge of the external input. ? register list input capture data register (ipcp0, ipcp1) control status register (ics01) 000045 h 000047 h initial value xxxxxxxx b read/write 000044 h 000046 h initial value xxxxxxxx b read/write 000048 h initial value 00000000 b read/write 15 14 13 12 11 10 9 8 rrrr rrr r cp14 cp15 cp13 cp12 cp11 cp10 cp09 cp08 7654 321 0 rrrr rrr r cp06 cp07 cp05 cp04 cp03 cp02 cp01 cp00 7654 321 0 r/w r/w r/w r/w r/w r/w r/w r/w icp0 icp1 ice1 ice0 eg11 eg10 eg01 eg00 mb90800 series 49 ? block diagram ic 0 eg11 eg10 eg01 eg00 icp1 icp0 ice1 ice0 ic 1 bus capture data register 0 16-bit timer counter value (t15 to t00) capture data register 1 edge detection edge detection interrupt #25 interrupt #25 mb90800 series 50 10. 16-bit reload timer the 16-bit reload timer provides two functions either one which can be selected, the internal clock mode that performs the count down by synchronizing with 3-type internal clocks and the event count mode that performs the count down by detecting the arbitr ation. this timer defi nes an underflow as a transi tion of the count value from 0000 h to ffff h . therefore, when the equation (counted value = reload register setting value + 1) holds, an underflow occurs. either mode can be selected for the count operation from the reload mode which repeats the count by reloading the count setting value at the underflow occurrence or the one-shot mode which stops the count at the underflow occurrence. the interrupt can be generated at the counter underflow occurrence so as to correspond to the dtc. (1) register list ? tmcsr timer control status register timer control status register (upper) (tmcsr0h to tmcsr2h) timer control status register (lower) (tmcsr0l to tmcsr2l) ? 16-bit timer register/16 - bit reload register tmr0 to tmr2/tmrlr0 to tmrlr2 (upper) tmr0 to tmr2/tmrlr0 to tmrlr2 (low) - : unused initial value 000051 h 000055 h 000059 h - - - - 0000 b read/write initial value 000050 h 000054 h 000058 h 00000000 b read/write initial value 000053 h 000057 h 00005b h xxxxxxxx b read/write initial value 000052 h 000056 h 00005a h xxxxxxxx b read/write ??? r/w r/w r/w r/w 15 14 13 12 11 10 9 8 ? ? ??? csl1 csl0 mod2 mod1 r/w r/w r/w r/w r/w r/w r/w 7654 3210 oute r/w mod0 outl reld inte uf cnte trg r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 d14 r/w d15 d13 d12 d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w 7654 3210 d6 r/w d7 d5 d4 d3 d2 d1 d0 mb90800 series 51 (2) block diagram tmrlr tmr en out e reld outl clk clk uf 3 3 2 internal data bus 16-bit reload register 16-bit timer register (down counter) count clock generation circuit machine clock prescaler valid clock identification circuit gate input clear pin input control circuit external clock select function select signal timer control status register (tmcsr) clock selector reload signal wait signal output signal generation circuit output signal generation circuit pin reload control circuit re- verse operation control circuit mb90800 series 52 11. watch timer the watch timer is a 15-bit timer using the subclock. it can generate the interrupt re quest for each interval time. the watch timer can also be us ed as the clock source of the watchdog timer by setting so. (1) register list (2) block diagram watch timer control register (wtc) initial value 0000aa h 1x011000 b read/write r r/w r/w r/w r/w r/w r/w 7654 3210 sce r/w wdcs wtie wtof wtr wtc2 wtc1 wtc0 wdcs sce wtie wtof wtr wtc2 wtc1 wtc0 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 10 2 13 2 14 2 15 sub clock watch counter interval selector interrupt generation circuit watch timer interrupt to watchdog timer watch timer control register (wtc) clear mb90800 series 53 12. watchdog timer the watchdog timer is a timer counter provided for prev enting program malfunction. the watchdog timer is a 2- bit counter operating with an output of the timebase ti mer or watch timer as count clock and resets the cpu when the counter is not cleared within the interval time. (1) register list (2) block diagram watchdog timer control register (wdtc) ? : unused initial value 0000a8 h xxxxx111 b read/write ? rrrwww 7654 3210 ? r ponr wrst erst srst wte wt1 wt0 ponr wrst erst srst wte wt1 wt0 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 1 sclk clr clr 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 4 4 watchdog timer control register (wdtc) watchdog timer watch mode start time-base timer mode start sleep mode start hold status start counter clear control circuit count clock selector 2-bit counter watchdog reset generation circuit clear internal reset generation circuit clr and start-up time base counter dividing hclk by 2 hclk: oscillation clock sclk: sub clock wdcs bit of watch timer control register (wto) scm bit of clock selection register (ckscr) stop mode start mb90800 series 54 13. time-base timer the time-base timer has a function that enables a selectio n of four interval times using 18-bit free-run counter (time-base counter) with synchronizing to the internal count clock (two divi sion of original oscillation). further- more, the function of timer output of oscillation stabilizat ion wait or function supp lying operation clocks for watchdog timer are provided. (1) register list (2) block diagram timer base timer control register (tbtc) - : unused initial value 0000a9 h 1 - - 00100 b read/write ?? r/w r/w w r/w r/w 15 14 13 12 11 10 9 8 ? r/w ? tbie tbof tbr tbc1 tbc0 reserved tbie tbof tbr reserved ?? tbc1 tbc0 of of of of 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 to ppg timer time-base timer counter dividing hclk by 2 to watchdog timer power-on reset counter clear control circuit interval timer selector tbof clear time-base timer control register (tbtc) time-base timer interrupt signal to clock controller oscillation stabilizing wait time selector tbof set ? : unused of : overflow hclk : oscillation clock *1 : the machine clock is switched from main/sub clock to pll clock. *2 : the machine clock is switched from sub clock to main clock. stop mode start hold status start ckscr : mcs = 0* 1 ckscr : scs = 0 1* 2 mb90800 series 55 14. clock generator the clock generator controls operation of the internal cl ock which is the operation clock for the cpu and peripheral devices. this internal clock is used as machine clock a nd its one cycle as machine cycle. in addition, the clock generated by original oscillation is used as oscillation cl ock and that by internal pll oscillation as pll clock. (1) register list clock selection register (ckscr) initial value 0000a1 h 11111100 b read/write r r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 mcm r scm ws1 ws0 scs mcs cs1 cs0 mb90800 series 56 (2) block diagram scm hclk sclk mcm ws1 ws0 scs mcs cs1 cs0 stp slp spl rst tmd cg1 cg0 2 2 x0a x1a r st x0 x1 mclk reserved low power consumption mode control register (lpmcr) release interrupting cpu intermittent operation selector pin high - z control circuit clock selector sub clock generation circui t pin oscillation stabilization wait time selector clock selection register (ckscr) time-base timer pin peripheral clock control circuit internal reset generation circuit standby control circuit pll multiplying circuit pin pin to watchdog timer dividing by 1024 hclk : oscillation clock mclk : main clock sclk : sub clock standby control circuit cpu clock control circuit pin system clock generation circuit dividing by 2 dividing by 2 dividing by 4 dividing by 4 dividing by 4 dividing by 2 clock generation block machine clock oscillation stabilization wait pin high - z control cpu clock internal reset stop, sleep signal stop signal peripheral clock intermittent cycle selection dividing by 4 mb90800 series 57 (3) clock supply map x0 x1 x 0a x 1a hclk mclk sclk cpu (f 2 mc-16lx) pclk 1234 clock generation circuit oscillation circuit watch timer timer clock divider watchdog timer oscillation circuit selector time-base timer internal resources lcd controller 16-bit reload timer 8/10-bit a/d converter serial i/o free-run timer input capture pll multiplying circuit 2 division circuit 2 division circuit selector rom/ram (memory) hclk : oscillation clock mclk : main clock pclk : pll clock sclk : sub clock mb90800 series 58 15. low power consumption mode the low-power consumption mode has the following cpu o peration modes by selecting the operation clock and operating the control of the clock. clock mode (pll clock mode, main clock mode and sub clock mode) cpu intermittent operation mode (pll clock intermittent operation mode, main clock inte rmittent operation mode and subclock intermittent operation mode) standby mode (sleep mode, time base timer mode, stop mode and watch mode) (1) register list low power consumption mode control register (lpmcr) initial value 0000a0 h 00011000 b read/write w r/w w r/w r/w r/w r/w 7654 3210 slp w stp spl rst tmd cg1 cg0 reserved mb90800 series 59 (2) block diagram scm hclk sclk mcm ws1 ws0 scs mcs cs1 cs0 stp slp spl rst tmd cg1 cg0 2 2 x0a x1a r st x0 x1 mclk reserved low power consumption mode control register (lpmcr) release of interrupt cpu intermittent operation selector pin high-z control circuit clock selector sub clock generation circuit pin oscillation stabilization wait time selector clock selection register (ckscr) time-base timer pin peripheral clock control internal reset generation circuit standby control circuit pll multiplying circuit pin pin to watchdog timer dividing by 1024 hclk : oscillation clock mclk : main clock sclk : sub clock standby control circuit cpu clock control circuit pin system clock generation circuit dividing by 2 dividing by 2 dividing by 4 dividing by 4 dividing by 4 dividing by 2 clock generation block machine clock release of oscillation stabilization wait pin high-z contro l cpu clock internal reset stop, sleep signal stop signal peripheral clock intermittent cycle selection dividing by 4 mb90800 series 60 (3) figure of status transition stp = 1 stp = 1 stp = 1 tmd = 0 tmd = 0 tmd = 0 slp = 1 slp = 1 slp = 1 mcs = 0 mcs = 1 scs = 0 scs = 0 scs = 1 scs = 1 power-on reset power supply end of oscillation stabilization wait main clock mode main sleep mode time-base timer mode main stop mode main clock oscillation stabilization wait pll clock mode pll sleep mode time-base timer mode pll stop mode main clock oscillation stabilization wait sub clock mode sub sleep mode watch mode sub stop mode sub clock oscillation stabilization wait interrupt interrupt interrupt interrupt interrupt interrupt end of oscillation stabilization wait reset external reset, watchdog timer reset, software reset, interrupt interrupt interrupt end of oscillation stabilization wait end of oscillation stabilization wait mb90800 series 61 16. timer clock output the timer clock output circuit divides the oscillation cloc k by the time-base timer and generates and outputs the set division clock. selectable from 32/ 64/128/256 division of the oscillation clock. the timer clock output circuit is inactive in reset or stop mode. it is active in normal run, sleep, or pseudo-timer mode. note : when the time-base timer is cleared while using the timer clock output circuit, the clock is not correctly output. for detail of the time-base timer?s clear condition, see the section of time- base timer in the mb90800 hardware manual. (1) register list (2) block diagram pll_run main_run sleep pseudo clock stop reset operation status watch clock output control register (tmcs) - : unused initial value 0000af h xxxxx000 b read/write r/w r/w r/w 15 14 13 12 11 10 9 8 ? ???? ten ts1 ts0 ? ???? x 0 x 1 timer clock selection circuit oscillation circuit timer clock output selector time-base timer dividing by 2 mb90800 series 62 17. rom mirroring function selection module rom mirrorring function selection module provides the setting so that rom data located in ff bank can be read by access to 00 bank. (1) register list (2) block diagram note : do not access to rom mirroring function selection register in the middle of the operation of the address 008000 h to 00ffff h . rom mirror function select register (romm) - : unused initial value 00006f h xxxxxxx1 b read/write r/w 15 14 13 12 11 10 9 8 mi rom address area rom mirroring function selection f 2 mc-16lx bus ff bank 00 bank address data mb90800 series 63 18. interrupt controller interrupt control register is in the interrupt controller. t he register corresponds to all i/o of interrupt function. the register has following functions; setting of interrupt level at correspondent peripheral circuit. (1) register list (at writing) note : do not access using read modify write instruction because it causes the malfunction. interrupt control register initial value address : icr01 icr03 icr05 icr07 icr09 icr11 icr13 icr15 0000b1 h 0000b3 h 0000b5 h 0000b7 h 0000b9 h 0000bb h 0000bd h 0000bf h 00000111 b read/write interrupt control register initial value address : icr00 icr02 icr04 icr06 icr08 icr10 icr12 icr14 0000b0 h 0000b2 h 0000b4 h 0000b6 h 0000b8 h 0000ba h 0000bc h 0000be h 00000111 b read/write 15 14 13 12 11 10 9 8 ics2 ics3 ics1 ics0 ise il2 il1 il0 w w w r/w r/w r/w r/w w bit 7654 3210 w w w r/w r/w r/w r/w ics2 w ics3 ics1 ics0 il2 il1 il0 ise bit mb90800 series 64 (2)register list (at reading) - : unused note : do not access using read modify write instruction because it c auses the malfunction. interrupt control register initial value address : icr01 icr03 icr05 icr07 icr09 icr11 icr13 icr15 0000b1 h 0000b3 h 0000b5 h 0000b7 h 0000b9 h 0000bb h 0000bd h 0000bf h - - 000111 b read/write read/write initial value interrupt control register initial value address : icr00 icr02 icr04 icr06 icr08 icr10 icr12 icr14 0000b0 h 0000b2 h 0000b4 h 0000b6 h 0000b8 h 0000ba h 0000bc h 0000be h - - 000111 b read/write read/write initial value 15 14 13 12 11 10 9 8 ? r r r/w r/w r/w r/w ? ? ? s1 s0 ise il2 il1 il0 bit 7654 3210 ? r r r/w r/w r/w r/w ? ? ? s1 s0 il2 il1 il0 ise bit mb90800 series 65 (3) block diagram il2 il1 il0 32 3 3 3 judging the priority of interrupt interrupt request (peripheral resources) (cpu) interrupt level f 2 mc-16lx bus mb90800 series 66 19. lcd controller/driver the lcd controller/driver contains 24 8-bit display data memory and contro ls the lcd display with four common output lines and 48 segment output lines. three duty outputs can be select ed to directly drive the lcd panel (liquid crystal display). contains an lcd driving voltage split resistor. moreov er, the external division resistance can be connected. a maximum of four common output lines (com0 to com3) and 48 segment out put lines (seg0 to seg47) are available. contains 24-byte display data memory (display ram). for the duty, 1/2, 1/3, or 1/4 can be selected (restricted by bias setting). the lcd can directly be driven. : recommended mode : disable (1) register list bias 1/2 duty 1/3 duty 1/4 duty 1/2 bias 1/3 bias ? lcr (lcd control register) lcd control register (higher) (lcrh) lcd control register (lower) (lcrl) ? lcdc range register (lcrr) initial value 00005d h 00000000 b read/write initial value 00005c h 00010000 b read/write initial value 00005e h 00000000 b read/write r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 vs0 r/w ss4 cs1 cs0 ss3 ss2 ss1 ss0 r/w r/w r/w r/w r/w r/w r/w 7654 3210 lcen r/w css vsel bk ms1 ms0 fp1 fp0 r/w r/w r/w r/w r/w r/w r/w 7654 3210 r/w se4 se3 se2 se1 se0 lcr reserved reserved mb90800 series 67 (2) block diagram 4 48 v0 v1 v2 v3 com 0 com 1 com 2 com 3 seg0 0 seg0 1 seg0 2 seg0 3 seg0 4 seg4 2 seg4 3 seg4 4 seg4 5 seg4 6 seg4 7 to internal data bus lcdc range register (lcrr) main clock sub clock (32 khz) lcd control register (lcrl) prescaler timing controller display ram 24 8-bit lcd control register (lcrh) division resistor controller driver circuit of making to exchange common driver segment driver mb90800 series 68 electrical characteristics 1. absolute maximum ratings *1 : the parameter is based on v ss = av ss = 0.0 v. *2 : av cc should not be exceeding v cc at power-on etc. *3 : v i , v o , should not exceed vcc + 0.3 v. *4 : applicable to pins : p74, p75 *5 : a peak value of an applicable one pin is specified as a maximum output current. *6 : an average current value of an applicable one pin wi thin 100 ms is specified as an average output current. (average value is found by multiplying operating current by operating rate.) *7 : an average current value of all pins within 100 ms is specified as an average total output current. (average value is found by multiplying operating current by operating rate.) warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss + 4.0 v av cc v ss ? 0.3 v ss + 4.0 v v cc av cc * 2 input voltage* 1 v i v ss ? 0.3 v ss + 4.0 v *3 v ss ? 0.3 v ss + 6.0 v n-ch open-drain (5 v withstand voltagei/o) * 4 output voltage* 1 v o v ss ? 0.3 v ss + 4.0 v *3 ?l? level maximum output current i ol11 ? 10 ma other than p74, p75, p40 to p47* 5 i ol12 ? 30 ma p74, p75, p40 to p47 (heavy-current output port) * 5 ?l? level average output current i olav1 ? 3ma other than p74, p75, p40 to p47* 6 i olav2 ? 15 ma p74, p75, p40 to p47 (heavy-current output port) * 6 ?l? level maximum total output current i ol ? 120 ma ?l? level average total output current i olav ? 60 ma *7 ?h? level maximum output current i oh11 ? ? 10 ma other than p74, p75, p40 to p47* 5 i oh12 ? ? 12 ma p40 to p47 (heavy-current output port) * 5 ?h? level average output current i ohav ? ? 3ma*6 ?h? level maximum total output current i oh ? ? 120 ma ?h? level average total output current i ohav ? ? 60 ma *7 power consumption pd ? 351 mw operating temperature t a ? 40 + 85 c storage temperature t stg ? 55 + 150 c mb90800 series 69 2. recommended operating conditions ( v ss = av ss = 0.0 v) warning: the recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 2.7 3.6 v at normal operating 1.8 3.6 v stop operation state maintenance ?h? level input voltage v ih 0.7 v cc v cc + 0.3 v cmos input pin v ihs 0.8 v cc v cc + 0.3 v cmos hysteresis input pin (resisting pressure of 5 v is v cc = 5.0 v) v ihm v cc ? 0.3 v cc + 0.3 v md pin input ?l? level input voltage v il v ss ? 0.3 0.3 v cc v cmos input pin v ils v ss ? 0.3 0.2 v cc v cmos hysteresis input pin v ilm v ss ? 0.3 v ss + 0.3 v md pin input operating temperature t a ? 40 + 85 c mb90800 series 70 3. dc characteristics (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name conditions value unit remarks min typ max ?h? level output voltage v oh output pins other than p40 to p47, p74, p75 i oh = ? 4.0 ma v cc ? 0.5 ? vcc v v oh1 p40 to p47 i oh = ? 8.0 ma v cc ? 0.5 ? vcc v heavy-current output port ?l? level output voltage v ol output pins other than p40 to p47, p74, p75 i ol = 4.0 ma vss ? vss + 0.4 v v ol1 p40 to p47 i ol = 15.0 ma vss ? vss + 0.6 v heavy-current output port v ol2 p74, p75 i ol = 15.0 ma ? 0.5 vss + 0.8 v open-drain pin open-drain output application voltage v d1 p74, p75 ? vss ? 0.3 ? vss + 5.5 v input leak current i il all output pin v cc = 3.3 v, v ss < v i < v cc ? 10 ?+ 10 a pull-up resistor r up rst vcc = 3.3 v, t a = + 25 c 25 50 100 k ? pull-down resistor r down md2 vcc = 3.3 v, t a = + 25 c 25 50 100 k ? except flash memory products open drain output current i leak p74, p75 ?? 0.1 10 a power supply current i cc v cc v cc = 3.3 v, internal fre- quency 25 mhz at normal oper- ating ? 48 60 ma v cc = 3.3 v, internal fre- quency 25 mhz at flash writing ? 60 75 ma flash memory products v cc = 3.3 v, internal fre- quency 25 mhz at flash erasing ? 60 75 ma flash memory products i ccs v cc = 3.3 v, internal fre- quency 25 mhz at sleep mode ? 22.5 30 ma mb90800 series 71 (continued) (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) * : lcd internal divided resistor can be select two type re sistor by internal divided resistor selecting bit (lcr) of lcdc range register (lcrr) . parameter sym- bol pin name conditions value unit remarks min typ max power supply current i ccts v cc v cc = 3.3 v, internal frequency 3 mhz at timer mode ? 0.75 7 ma i ccl v cc = 3.3 v, internal frequency 8 khz at subclock operation, (t a = + 25 c) ? 15 140 a mask rom products ? 0.5 0.9 ma flash memory products i ccls v cc = 3.3 v, internal frequency 8 khz at subclock sleep operation, (t a = + 25 c) ? 23 40 a i cct v cc = 3.3 v, internal frequency 8 khz at watch mode (t a = + 25 c) ? 1.8 40 a i cch at stop mode, (t a = + 25 c) ? 0.8 40 a lcd division resistance r lcd v cc ? v3 at lcr = 0 setting 100 200 400 k ? * v cc ? v3 at lcr = 1 setting 12.5 25 50 v0 ? v1, v1 ? v2, v2 ? v3 at lcr = 0 setting 50 100 200 v0 ? v1, v1 ? v2, v2 ? v3 at lcr = 1 setting 6.25 12.5 25 com0 to com3 output impedance r vcom com0 to com3 v1 to v3 = 3.3 v ?? 2.5 k ? seg00 to seg47 output impedance r vseg seg00 to seg47 ?? 15 k ? lcd leak current i lcdc v0 to v3, com0 to com3, seg00 to seg47 ?? 5 ?+ 5 a mb90800 series 72 4. ac characteristics (1) clock timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym bol pin name condi- tions value unit remarks min typ max clock frequency f ch x0, x1 ? 3 ? 16 mhz external crystal oscillation f ch 316 1/2 (at pll stop) at oscillation circuit 416 multiply by 1 at oscillation circuit 412.5 multiply by 2 at oscillation circuit 48.33 multiply by 3 at oscillation circuit 46.25 multiply by 4 at oscillation circuit x0 325 1/2 (at pll stop) at external clock 425 multiply by 1 at external clock 412.5 multiply by 2 at external clock 48.33 multiply by 3 at external clock 46.25 multiply by 4 at external clock f cl x0a, x1a ? 32.768 ? khz clock cycle time t hcyl x0, x1 40 ? 333 ns t lcyl x0a, x1a ? 30.5 ? s input clock pulse width p wh p wl x0 5 ?? ns set duty ratio 50 % 3 % p wlh p wll x0a ? 15.2 ? s set duty ratio at 30 % to 70 % as a guideline. input clock rise time and fall time tcr tcf x0 ?? 5 ns at external clock internal operating clock frequency f cp ? 1.5 ? 25 mhz when main clock is used f cp1 ?? 8.192 ? khz when sub clock is used internal operating clock cycle time t cp ? 40 ? 666 ns when main clock is used t cp1 ?? 122.1 ? s when sub clock is used mb90800 series 73 0.8 v c c 0.2 v c c t cf t cr t c p wh p wl ? x0, x1 clock timing 0.8 v c c 0.2 v c c t cf t cr t cl p wlh p wll ? x0a, x1a clock timing mb90800 series 74 rating values of alternating current is defined by th e measurement reference volt age values shown below : ? pll operation guarantee range relation between internal operation cloc k frequency and power supply voltage relation between oscillation clock frequenc y and internal operating clock frequency 3 .6 3 .0 2 .7 1.5 4.5 16 25 pll operation guarantee range normal operation assurance range internal operation clock f cp (mhz) power voltage v cc (v) 25 16 12 8 6 4 .5 4 3 4 4.5 6 8 12 16 25 multiply by 4 multiply by 3 multiply by 2 multiply by 1 original oscillation clock f ch (mhz) internal operation clock f cp (mhz) external clock 1/2 (pll off ) 0 .8 v cc 0 .2 v cc 2.4 v 0.8 v ? input signal waveform hysteresis input pin ? output signal waveform output pin mb90800 series 75 (2) reset input timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) * : oscillation time of oscillator is time until oscillation reaches 90% of amplitude. it takes several milliseconds to several dozens of milliseconds on a crystal oscillator, se veral hundreds of microseconds to several milliseconds on a far/ceramic oscillator, and 0 milliseconds on an external clock. parameter sym- bol pin name condi- tions value unit remarks min max reset input time t rstl rst ? 500 ? ns at normal operating, at time base timer mode, at main sleep mode, at pll sleep mode oscillation time of oscillator* + 500 ns ? s at stop mode, at sub clock mode, at sub sleep mode, at watch mode r st x0 500 ns t rstl 0.2 v cc 0.2 v cc r st t rstl 0.2 v cc 0.2 v cc ? in normal operating, time base timer mode, main sleep mode and pll sleep mode ? in stop mode, sub clock mode, sub sleep mode and watch mode internal operating clock internal reset 90 % of amplitude oscillation time of oscillator wait time for stabilization oscillator execute instruction mb90800 series 76 (3) power-on reset (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) notes : ? v cc should be set under 0.2 v before power-on rising up. ? these value are for power-on reset. ? in the device, there are internal registers which is initialized only by a power-on reset. if these initialization is executing, power-on procedure must be obeyed by these value. note : sudden change of power supply voltage may activate the power-on re set function. when changing power supply voltages during operation, raise the power smoot hly by suppressing variation of voltages as shown below. parameter symbol pin name condi- tions value unit remarks min max power supply rising time t r v cc ? ? 30 ms at normal operating power supply shutdown time t off v cc 1 ? ms wait time until power on v cc t r 0.2 v 0.2 v 2.7 v t off 0.2 v v cc 2 .7 0.3 v v ss ram data hold limiting the slope of rising within 50 mv/ms is recommended. mb90800 series 77 (4) serial i/o (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) notes : ? the above rating is in clk synchronous mode. ? c l is a load capacitance value on pins for testing. ? t cp is machine cycle frequency (ns) . refer to ? (1) clock timing?. parameter sym bol pin name conditions value unit remarks min max serial clock cycle time t scyc sc0 to sc3 internal shift clock mode output pin : c l = 80 pf + 1ttl 8 t cp ? ns sck sot delay time t slov sc0 to sc3, so0 to so3 ? 80 80 ns valid sin sck t ivsh sc0 to sc3, si0 to si3 100 ? ns sck valid sin hold time t shix 60 ? ns serial clock h pulse width t shsl sc0 to sc3 external shift clock mode output pin : c l = 80 pf + 1ttl 4 t cp ? ns serial clock l pulse width t slsh 4 t cp ? ns sck sot delay time t slov sc0 to sc3, so0 to so3 ? 150 ns valid sin sck t ivsh sc0 to sc3, si0 to si3 60 ? ns sck valid sin hold time t shix 60 ? ns ? internal shift clock mode ? external shift clock mode s c s o s i t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc s c s o s i t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc mb90800 series 78 (5) timer input timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) note : t cp is machine cycle frequency (ns) . refer to ? (1) clock timing?. (6) timer output timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) (7) trigger input timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) note : t cp is machine cycle frequency (ns) . refer to ? (1) clock timing?. parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh t tiwl tin0 to tin2, ic0, ic1 ? 4 t cp ? ns parameter sym- bol pin name condi- tions value unit remarks min max clk t out change time t to tot0 to tot2, ppg0, ppg1, ocu0, ocu1 ? 30 ? ns parameter symbol pin name condi- tions value unit remarks min max input pulse width t trgh t trgl int0 to int3 ? 5 t cp ? ns at normal operating 1 ? sin stop mode 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl t inx i cx ? timer input timing c lk t otx p pgx o cux 2.4 v t to 2.4 v 0.8 v ? timer output timing 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl i ntx ? trigger input timing mb90800 series 79 (8) i 2 c timing (av cc = v cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : f cp is internal operation clock frequency. refer to ? (1) clock timing?. *2 : r, c : pull-up resistor and lo ad capacitor of the scl and sda lines. *3 : the maximum t hddat only has to be met if the devi ce does not stretch the ?l? width (t low ) of the scl signal. *4 : refer to ? ? note of sda and scl set-up time?. parameter symbol conditions standard- mode unit min max scl clock frequency f scl when power supply voltage of external pull-up resistor is 5.0 v r = 1.0 k ? , c = 50 pf* 2 when power supply voltage of external pull-up resistor is 3.6 v r = 1.0 k ? , c = 50 pf* 2 0100khz hold time (repeated) start condition sda scl t hdsta 4.0 ? s ?l? width of the scl clock t low 4.7 ? s ?h? width of the scl clock t high 4.0 ? s set-up time for a repeated start condition scl sda t susta 4.7 ? s data hold time scl sda t hddat 0 3.45 * 3 s data set-up time sda scl t sudat when power supply voltage of external pull-up resistor is 5.0 v f cp * 1 20 mhz, r = 1.0 k ? , c = 50 pf* 2 when power supply voltage of external pull-up resistor is 3.6 v f cp * 1 20 mhz, r = 1.0 k ? , c = 50 pf* 2 250 * 4 ? ns when power supply voltage of external pull-up resistor is 5.0 v f cp * 1 > 20 mhz, r = 1.0 k ? , c = 50 pf* 2 when power supply voltage of external pull-up resistor is 3.6 v f cp * 1 > 20 mhz, r = 1.0 k ? , c = 50 pf* 2 200 * 4 ? ns set-up time for stop condition scl sda t susto when power supply voltage of external pull-up resistor is 5.0 v r = 1.0 k ? , c = 50 pf* 2 when power supply voltage of external pull-up resistor is 3.6 v r = 1.0 k ? , c = 50 pf* 2 4.0 ? s bus free time between a stop and start condition t bus 4.7 ? s mb90800 series 80 note : the rating of the input data set- up time in the device connected to the bus cannot be satisfied depending on the load capacitance or pull-up resistor. be sure to adjust the pull-up resistor of sda and scl if the rating of the input data set-up time cannot be satisfied. sda scl 6 tcp ? note of sda and scl set-up time input data set-up time sda scl t bus t low f scl t hddat t high t sudat t hdsta t susta t hdsta t susto ? timing definition mb90800 series 81 5. electrical characteristics for the a/d converter (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : at operating, main clock 25 mhz. *2 : if a/d converter is not operating, a curr ent when cpu is stopped is applicable (at vcc ? cpu = avcc = 3.3 v) parameter sym- bol pin name value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb nonlinear error ?? ? ? 2.5 lsb differential linear error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an11 av ss ? 1.5 lsb avss + 0.5 lsb av ss + 2.5 lsb mv 1 lsb = avcc/1024 full-scale transition voltage v fst an0 to an11 avcc ? 3.5 lsb avcc ? 1.5 lsb avcc + 0.5 lsb mv conversion time ?? 8.64* 1 ?? s sampling time ?? 2 ?? s analog port input current i ain an0 to an11 ?? 10 a analog input voltage v ain an0 to an11 0 ? avcc v reference voltage ? avcc 3.0 ? avcc v power supply current i a avcc ? 1.4 3.5 ma i ah avcc ?? 5* 2 a reference voltage supplying current i r avcc ? 94 150 a i rh avcc ?? 5* 2 a interchannel disparity ? an0 to an11 ?? 4lsb mb90800 series 82 about the external impedance of an alog input and its sampling time> a/d converter with sample and hold circuit. if the exter nal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. therefore, to satisfy the a/d conversion precision standard, consider the relation-ship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. and, if the sampling time ca nnot be sufficient, connect a capacitor of about 0.1 f to the analog input pin. about errors as | avrh ? av ss | becomes smaller, values of relative errors grow larger. ? analog input circuit model r c comparator analog input rc mb90802 (s)/803 (s) 1.9 k ? (max) 32.3 pf (max) mb90f804 1.9 k ? (max) 25.0 pf (max) mb90v800 1.9 k ? (max) 32.3 pf (max) note : the values are reference values. during sampling : on 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 mb90802(s)/ mb90803(s)/ mb90v800 35 mb90f804 mb90802(s)/ mb90803(s)/ mb90v800 20 18 16 14 12 10 8 6 4 2 0 012345 78 mb90f804 6 (external impedance = 0 k ? to 100 k ? ) (external impedance = 0 k ? to 20 k ? ) minimum sampling time [ s] minimum sampling time [ s] external impedance [k ? ] external impedance [k ? ] ? the relationship between external impedance and minimum sampling time mb90800 series 83 6. definition of a/d converter terms resolution analog variation that is recognized by an a/d converter. the 10-bit can resolve analog voltage into 2 10 = 1024. total error this shows the difference between the actual voltage a nd the ideal value and means a total of error because of offset error, gain error, non-linearity error and noise. linearity error deviation between a line across zero-transition line (00 0000 0000 ? 00 0000 0001) and full-scale transition line (11 1111 1110 ? 11 1111 1111) and actual conversion characteristics. differential linear error deviation of input voltage, which is required for ch anging output code by 1 lsb, from an ideal value. (continued) 3 ff h 3 fe h 3 fd h 004 h 003 h 002 h 001 h av ss (avrl) av cc (avrh) 0.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb } total error digital output actual conversion characteristic v nt (measurement value) analog input total error of digital output n = v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb v ot (ideal value) = av ss + 0.5 lsb [v] v fst (ideal value) = av cc ? 1.5 lsb [v] 1lsb(ideal value) = av cc ? av ss 1024 [v] actual conversion characteristics ideal characteristics [lsb] v nt : a voltage at which digital output transitions from (n ? 1) to n. n : a/d converter digital output value mb90800 series 84 (continued) linear error in digital output n = v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] differential linear error in digital output n = v (n + 1) t ? v nt 1 lsb ? 1lsb 1 lsb = v fst ? v ot 1022 [v] v fst : voltage at which digital output transits from 3fe h to 3ff h . n ? 1 av ss (avrl) av cc (avrh) n ? 2 n n + 1 actual conversion characteristic ideal characteristics v (n + 1)t (measurement value) v nt (measurement value) actual conversion characteristics linearity error differential linear error digital output digital output analog input analog input v ot : voltage at which digital output transits from 000 h to 001 h . [lsb] 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss (avrl) av cc (avrh) actual conversion characteristics {1 lsb (n ? 1) + v ot } v fst v nt actual conversion characteristics ideal characteristics v ot (actual measurement value) (measurement value) (measurement value) n : a/d converter digital output value mb90800 series 85 7. flash memory * : this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c). parameter conditions value unit remarks min typ max sector erase time t a = + 25 c vcc = 3.0 v ? 115s excludes 00 h programming prior to erasure. chip erase time ? 9 ? s excludes 00 h programming prior to erasure. word (16-bit width) programming time ? 16 3600 s except for the over head time of the system. program/erase cycle ? 10000 ?? cycle flash memory data retention time average t a = + 85 c 20 ?? year * mb90800 series 86 ordering information part number package remarks mb90f804-101pf-g mb90f804-201pf-g 100-pin plastic qfp (fpt-100p-m06) mb90803pf-g mb90803spf-g mb90802pf-g MB90802SPF-G mb90800 series 87 package dimension 100-pin plastic qfp (fpt-100p-m06) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins th ickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) . note : the values in parentheses are reference values. c 2002 fujitsu limited f100008s-c-5-5 1 30 31 50 51 80 81 100 20.000.20(.787.008) 23.900.40(.941.016) 14.000.20 (.551.008) 17.900.40 (.705.016) index 0.65(.026) 0.320.05 (.013.002) m 0.13(.005) "a" 0.170.06 (.007.002) 0.10(.004) details of "a" part (.035.006) 0.880.15 (.031.008) 0.800.20 0.25(.010) 3.00 +0.35 ?0.20 +.014 ?.008 .118 (mounting height) 0.250.20 (.010.008) (stand off) 0~8 ? * * mb90800 series f0604 the information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/mic roelectronics/product/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. edited business promotion dept. |
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